1. Technical Field
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and a driving method thereof that are capable of automatically selecting a common voltage to supply it to a common electrode of liquid crystal cells.
2. Description of the Related Art
A liquid crystal display device (LCD) controls light transmittance of liquid crystal cells based on video signals to thereby display a picture. An active matrix type of liquid crystal display device with a switching device provided for each liquid crystal cell is advantageous for an implementation of moving pictures because it permits an active control of the switching device. The switching device used for the active matrix liquid crystal display device may employ a thin film transistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.
Referring to FIG. 1, the active matrix LCD converts a digital input data into an analog data voltage based on a gamma reference voltage to supply it to a data line DL and, at the same time, supplies a scanning pulse to a gate line GL to thereby charge a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL while a source electrode thereof is connected to the data line DL. Further, a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to one electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
The storage capacitor Cst charges a data voltage fed from the data line DL when the TFT is turned-on, thereby constantly keeping a voltage at the liquid crystal cell Clc.
If the scanning pulse is applied to the gate line GL, then the TFT is turned on to provide a channel between the source electrode and the drain electrode thereof, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. In this case, liquid crystal molecules of the liquid crystal cell have an alignment changed by an electric field between the pixel electrode and the common electrode to thereby modulate an incident light.
A configuration of the related art LCD including pixels having the above-mentioned structure will be described with reference to FIG. 2. FIG. 2 is a block diagram showing a configuration of a general liquid crystal display device. Referring to FIG. 2, a general liquid crystal display device 100 includes a liquid crystal display panel 110 provided with a thin film transistor (TFT) that drives the liquid crystal cell Clc at an intersection of data lines DL1 to DLm and gate lines GL1 to GLn crossing each other, a data driver 120 that supplies data to the data lines DL1 to DLm of the liquid crystal display panel 110, a gate driver 130 that supplies a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110, a gamma reference voltage generator 140 that generates a gamma reference voltage to supply it to the data driver 120, a common voltage generator 150 that generates a common voltage Vcom to supply it to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110, a gate driving voltage generator 160 that generates a gate high voltage VGH and a gate low voltage VGL to supply them to the gate driver 130, and a timing controller 170 that controls the data driver 120 and the gate driver 130.
The liquid crystal display panel 110 has a liquid crystal injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other. Each intersection between the data lines DL1 to DLm and the gate lines GL1 to GLn is provided with the TFT. The TFT supplies a data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn while the source electrode thereof is connected to the data line DL1 to DLm. Further, the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst.
The TFT is turned-on in response to the scanning pulse applied, via the gate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on of the TFT, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc. The data driver 120 supplies data to the data lines DL1 to DLm based on a data driving control signal DDC supplied from the timing controller 170. Further, the data driver 120 samples and latches a digital video data RGB fed from the timing controller 170, and then converts it into an analog data voltage capable of expressing a gray scale level at the liquid crystal cell Clc of the liquid crystal display panel 110 based on a gamma reference voltage from the gamma reference voltage generator 140, thereby supplying it the data lines DL1 to DLm.
The gate driver 130 sequentially generates a scanning pulse, that is, a gate pulse in response to a gate driving control signal GDC and a gate shift clock GSC supplied from the timing controller 170 to supply them to the gate lines GL1 to GLn. In this case, the gate driver 130 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL from the gate driving voltage generator 160.
The gamma reference voltage generator 140 receives a power supply voltage VCC of 0V to 3.3V supplied from a system installed the liquid crystal display device 100, for example, a controller (not shown) of an image display apparatus such as a TV set, etc to generated a positive gamma reference voltage and a negative gamma reference voltage and output them to the data driver 120.
The common voltage generator 150 receives the power supply voltage VCC to generate a common voltage Vcom, and supplies it to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 160 is applied with the power supply voltage VCC of 3.3V supplied from the system to generate the gate high voltage VGH and the gate low voltage VGL, and supplies them to the gate driver 130. Herein, the gate driving voltage generator 160 generates a gate high voltage VGH more than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL less then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used to determine a high level voltage and a low level voltage of the scanning pulse generated by the gate driver 130, respectively.
The timing controller 170 supplies a digital video data RGB supplied from a digital video card (not shown) to the data driver 120 and, at the same time, generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronizing signals H and V in response to a clock signal CLK to supply them to the data driver 120 and the gate driver 130, respectively. Herein, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL and a source output enable signal SOE, or other signals, and the gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE, or other signals. The timing controller 170 generates a gate shift clock GSC to adjust a swing width of a gate pulse output from the gate driver 130 to supply it to the gate driver 130. In this case, a high-level voltage and a low-level voltage of the gate shift clock GSC is 3.3V and 0V, respectively. If the gate shift clock GSC is supplied, then the gate driver 130 determines a high-level voltage and a low-level voltage of the gate pulse using the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 160 in accordance with the gate shift clock GSC.
As described above, since a related art liquid crystal display device always supplies a constant common voltage to a common electrode of liquid crystal cells Clc regardless of a scan line system such as a phase-alternating line (PAL) system driven with a frequency of 50 Hz or a National Television Systems Committee NTSC system driven with a frequency of 60 Hz, there is raised a problem in that a flicker and a residual image are generated on the screen.